METHOD OF REALIZATION OF A HARDWARE LAYER                                               OF VLIW ARCHITECTURE ON THE BASIS SYSTOLIC STRUCTURES 

Fedyunin Roman Nikolaevich, Candidate of engineering sciences, associate professor, sub-department of computer science, Penza State University (Penza, 40 Krasnaya str.), frn_penza@mail.ru 

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The article describes a method of realization of arithmetic logic unit (ALU) of dedicated processors on the basis of VLIW architecture. The author describes ALU functional blocks for realization of basic arithmetic logic operations,
introduces a variant of realization of a universal cell which is the base for ALU computing core construction and gives the examples of ALU data processing computing schemes. The results of the research are the patent competitive solutions that have been practically implemented in research and production solution on the basis of industrial enterprises of Penza. Promissory nature of the solution is proved by multiple articles in foreign and Russian scientific press as well as by technical solutions of such corporations as XILINX and ALTERA. 

systolic computing, VLIW, pipeline computing, pipeline multiplication. 

1. Pat. RF 2284568. Yacheyka odnorodnoy vychislitel'noy sredy [Homogeneous computer medium cell]. Fedyunin R. N., Knyaz'kov V. S. 27.09.2006, no. 27.
2. Pat. RF 2285285. Yacheyka odnorodnoy sredy [Homogeneous medium cell]. Fedyunin R. N., Knyaz'kov V. S. 10.10.2006, no. 28.
3. Fedyunin R. N. Sistemnyy analiz, upravlenie i obrabotka informatsii [System analysis, control and processing of data]. 2006, Spetsvypusk, pp. 121–130.
4. available at: www.transmeta.com
5. available at: www.xilinx.com